5. The counter trigger pulse needs to be synchronous with the main timing clock. 6. Counter...

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5. The counter trigger pulse needs to be synchronous with the main timing clock. 6. Counter outputs feed the multiplexer Select inputs to control the multiplexer. 7. Retiming of the multiplexer output with a D-type flip-flop may be necessary to eliminate 'glitches' at bit transitions. (Where might these come from?) 5. The counter trigger pulse needs to be synchronous with the main timing clock. 6. Counter outputs feed the multiplexer Select inputs to control the multiplexer. 7. Retiming of the multiplexer output with a D-type flip-flop may be necessary to eliminate 'glitches' at bit transitions. (Where might these come from?)