Question: 5. Tomasulo Algorithm [15 points] Consider the following sequence of instructions. The table shows the execution time for each instruction LD 2 MULT.D F2,F1,FI 13:
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5. Tomasulo Algorithm [15 points] Consider the following sequence of instructions. The table shows the execution time for each instruction LD 2 MULT.D F2,F1,FI 13: LD I4 ADD.D I5 F1.0(RI) F3,8(RI) F4,F1,F1 F1,F3,F3 ADD.D Instruction LD ADD.D MULT.D Branch Execution time 4 Now schedule the code for a single-issue Tomasulo-style pipeline processor. - Assume only one reservation station entry for the load buffer, integer unit, floating point adder, floating point multiplier, store unit. - Assume that vou have one common data bus, - Assume an entry is usable again one cycle after CDB broadcast when reservation station entries are full. - If two results need to be broadcasted at the same cycle, earlier instruction has the precedence. - If an instruction is waiting for an operand in the reservation station, its execution starts one cycle after CDB broadcast. 5. Tomasulo Algorithm [15 points] Consider the following sequence of instructions. The table shows the execution time for each instruction LD 2 MULT.D F2,F1,FI 13: LD I4 ADD.D I5 F1.0(RI) F3,8(RI) F4,F1,F1 F1,F3,F3 ADD.D Instruction LD ADD.D MULT.D Branch Execution time 4 Now schedule the code for a single-issue Tomasulo-style pipeline processor. - Assume only one reservation station entry for the load buffer, integer unit, floating point adder, floating point multiplier, store unit. - Assume that vou have one common data bus, - Assume an entry is usable again one cycle after CDB broadcast when reservation station entries are full. - If two results need to be broadcasted at the same cycle, earlier instruction has the precedence. - If an instruction is waiting for an operand in the reservation station, its execution starts one cycle after CDB broadcast
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