5.1 Files Analysis You will start up by analyzing the files .bdf which you are provided with. You can do it either by using Quartus II, or by deciphering the diagrams at the end of this document (Fig. 3 - 11). You dont have to understand in detail the RAM operation (ram256x8), nor the controller of the 7-segment display. The diagram of the 4 bit SC counter is not included in the figures below, because the counter has the same architecture like the 8 bit counter, but truncated to 4 bits. Finally, the VHDL code of the bus multiplexer is presented in Table 7. Although you did not learn VHDL yet, you will see that the code is easy to understand, and much simpler to implement than would be a .bdf. Examining the logic diagrams, answer the following questions and write your answers in your report:

1. Draw a diagram which shows the hierarchy of the files, with lab3top at the top. For the files lab3controller, ram256x8, and sevensegcontroller, you do not have to identify the subfiles.

2. How can you check by analysing these files that only one register will place its output on the data bus at a time?

3. Are the register reset (clear) signals synchronous or asynchronous? Explain your answer. Note that all the command signals are active at high (i.e. a 1 will reset a register to 0).

4. What happens if a load and a reset are simultaneously sent to a register? Why?

5. Why the address register is connected directly to the memory?

6. Why the Program Counter, the Data Register, and the Accumulator are implemented as counters?

7. Of all the three commands of the counters (reset, increment, and load), which one has the highest priority? Which one has the lowest priority? Explain your answer.

8. Is it possible to read a value from memory directly to the accumulator? Explain your answer.

9. Analyze the ALU and determine a truth table which describes the 8 operations which can be selected by the three control lines. Are the shift operations logical or arithmetic?