$(\%)6.$ c$)$ Design the required memory device circuit diagram below. Add the minimum number

$8$ min

of additional memory components and SSI gates necessary $($no MSI gates, LSI gates or

PLDs$).$ Add memory components and address and data subscripts as needed; cross out

unneeded address and data pins. Use labels instead of wires for the design. Also, write

the equations for each CS at the bottom of the page. Show all connections with either

labels or wires $($labels are preferred$),$ just as in Quartus. Don't forget the system's

active$-$low chip enable, $CE,$ and $\frac{R}{}W[$pronounced read, write not, with $R(H)$ and

W$($L$)].$