$6.$ Consider the data$-$flow graph shown below:

Assume the following parameter values for FPGA implementation:

$-$ Multiplication requires $50$ clock cycles, Addition requires $20$ clock cycles, comparison requires $15$ clock cycles and the multiplexing operation requires $10$ clock cycles.

$-$ Multiplier requires $100$ LUTs, Adder requires $20$ LUTs, comparator requires $10$ LUTs and the Multiplexer requires $8$ LUTs.

$($a$)$ Draw the sequencing graph for the above data$-$flow graph. $[2$M$]$

$($b$)$ For an FPGA with $150$ LUTs, apply list scheduling based temporal partitioning algorithm for partitioning the sequencing graph in $($a$).($Assume priority is assigned based on number of successors$)($Clearly show which nodes are mapped to which partition$)[5$M$]$

$($c$)$ Calculate the quality of the partitioning obtained in $($b$).[2$M$]$

$($d$)$ Calculate the wasted resources for the partitioning obtained in $($b$),$ by clearly showing the graph of LUT utilization with respect to run time for each partition $($For each node in a partition, mark LUT usage on X$-$axis and runtime on Y$-$axis$).[7$M$]$