6. In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250 ps 350 ps 150 ps 300 ps 200 ps em m em Also, assume that instructions executed by the processor are broken down as follows: ALU Branch/Jump LDUR STUR 45% 20% 20% 15% (a) What is the clock cycle time in a pipelined and non-pipelined processor? (b) What is the total latency of an LDUR instruction in a pipelined and non-pipelined processor? (c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (d) Assuming there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit?