$6.\backslash ([\backslash$mathbf$\{30$ M$\}]\backslash )$ All the subparts of this question are related to the implementation of quadratic root of an equation $\backslash (\backslash$left$(\backslash$frac$\{\backslash$sqrt$\{$b$^\{2\}-4$ a c$\}-$b$\}\{2$ a$\}\backslash$right$)\backslash ).$ Assume the following:

$-$ Multiplication requires $200$ clock cycles, Addition$/$subtraction requires $100$ clock cycles, the division requires $500$ clock cycles and square root requires $1000$ clock cycles.

$-$ For FPGA implementation, multiplication, addition$/$subtraction$,$ division, and square root operation requires $\backslash (300,200,500\backslash ),$ and $800$ LUTs respectively.

$($a$)$ Draw the sequencing graph for the implementation of the quadratic root. $[4$M$]$

$($b$)$ Schedule $($determine the start time for$)$ each of the nodes of the above sequencing graph $($obtained in $($a$))$ using the ASAP algorithm. $[4$M$]$

$($c$)$ Using the maximum latency obtained in the ASAP algorithm, Schedule $($determine the start time for$)$ each of the nodes of the above sequencing graph $($obtained in $($a$))$ using the ALAP algorithm. $[4$M$]$

$($d$)$ For an FPGA with $1000$ LUTs, apply list scheduling based temporal partitioning algorithm for partitioning the sequencing graph in $($a$).($Assume priority is assigned based on number of successors$)[8$M$]$

$($e$)$ Calculate the quality of the partitioning for the one obtained in $($d$).[4$M$]$

$($f$)$ Calculate the wasted resources for the partitioning obtained in $($d$).[6$M$]$