6. One CPU manufacturer proposed the 10-stage pipeline below for a 500MHz (2ns clock cycle) machine....

  

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6. One CPU manufacturer proposed the 10-stage pipeline below for a 500MHz (2ns clock cycle) machine. IPG FET ROT (A) EXP REN WLD REG 1 2 4 5 6 7 Here are the correspondences between this and the MIPS pipeline: - Instructions are fetched in the FET stage. - Register reading is performed in the REG stage. 3 EXE 8 DET WRB - 9 -10 REG * - ALU operations and memory access are both done in the EXE stage. - Branches are resolved in the DET stage. - WRB is the writeback stage. How much time is required to execute one million instructions on this processor, o assuming there are no dependencies or branches in the code? (3%) (t+1)us (B) Without forwarding, how many stall cycles are needed for the following code fragment? Assume that the register file could be written and read in the same clock-eycle. (3 points) What is this hazard called? (3%) EXE, DET. data hasard 1lw $t0, 0 ($a0) add $v1, $t0, $to (C) If a branch is mispredicted, how many instructions would have to be flushed from the pipeline? (3%) FET DET. (Assume not written and read in ito (D) Assume that a program executes one million instructions. Of these, 15% are load instructions which stall, and 10% of the instructions are branches. The CPU predicts branches correctly 75% of the time. How much time will it take to execute this program? /+15% 22018 bubdle + 119 6. One CPU manufacturer proposed the 10-stage pipeline below for a 500MHz (2ns clock cycle) machine. IPG FET ROT (A) EXP REN WLD REG 1 2 4 5 6 7 Here are the correspondences between this and the MIPS pipeline: - Instructions are fetched in the FET stage. - Register reading is performed in the REG stage. 3 EXE 8 DET WRB - 9 -10 REG * - ALU operations and memory access are both done in the EXE stage. - Branches are resolved in the DET stage. - WRB is the writeback stage. How much time is required to execute one million instructions on this processor, o assuming there are no dependencies or branches in the code? (3%) (t+1)us (B) Without forwarding, how many stall cycles are needed for the following code fragment? Assume that the register file could be written and read in the same clock-eycle. (3 points) What is this hazard called? (3%) EXE, DET. data hasard 1lw $t0, 0 ($a0) add $v1, $t0, $to (C) If a branch is mispredicted, how many instructions would have to be flushed from the pipeline? (3%) FET DET. (Assume not written and read in ito (D) Assume that a program executes one million instructions. Of these, 15% are load instructions which stall, and 10% of the instructions are branches. The CPU predicts branches correctly 75% of the time. How much time will it take to execute this program? /+15% 22018 bubdle + 119

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The image depicts a question about a 10stage pipeline CPU architecture and its impact on the execution time of instructions It is asking for detailed analysis on different aspects of pipeline executio... View the full answer