$6.$ Problem $17\mathrm{.}8$ on page $652.$

$17\mathrm{.}8$ a$.$ Consider a uniprocessor with separate data and instruction caches, with hit ratios of $\backslash ($ H$\_\{$d$\}\backslash )$ and $\backslash ($ H$\_\{$t$\}\backslash ),$ respectively. Access time from processor to cache is $\backslash ($ c $\backslash )$ clock cycles, and transfer time for a block between memory and cache is $\backslash ($ b $\backslash )$ clock cycles. Let $\backslash ($ f$\_\{$i$\}\backslash )$ be the fraction of memory accesses that are for instructions, and $\backslash ($ f$\_\{$d$\}\backslash )$ is the fraction of dirty lines in the data cache among lines replaced. Assume a write$-$back policy and determine the effective memory access time in terms of the parameters just defined.

b$.$ Now assume a bus$-$based SMP in which each processor has the characteristics of part $($a$).$ Every processor must handle cache invalidation in addition to memory reads and writes This affects effective memory access time. Let $\backslash ($ f$\_\{\backslash$text $\{$tny $\}\}\backslash )$ be the fraction of data references that cause invalidation signals to be sent to other data caches. The processor sending the signal requires $\backslash ($ t $\backslash )$ clock cycles to complete the invalidation operation. Other processors are not involved in the invalidation operation. Determine the effective memory access time.