$6)$ Suppose that we are implementing a $1$ G x $8(1$ G registers, each with $8$ bits$)$ register file with one write$-$port and one read$-$port.

a$)$ How many and what type of decoder$($s$)$ would be needed?

b$)$ How many total gates $($assume $9-$input limit on AND & OR gates$)$ would be needed to implement this $($these$)$ decoder$($s$)?$

c$)$ How many and what type of MUX$($s$)$ would be needed?

d$)$ How many total gates $($assume $9-$input limit on AND & OR gates$)$ would be needed to implement this $($these$)$ MUX$($s$)?$

e$)$ Assuming $D$ flip$-$flops to store each bit $(4$ gates$/$flip$-$flop$).$ What $\%$ of the total gates is used to implement the $D$ flip$-$flops? The formula for this would be:Redo the previous question using the $1$ G x $8$ square$-$memory implementation similar to the $$Implementation of Large Memory Chips$$ section of Supplement #$5.$

For part $($e$),$ assume dynamic memory is used to store each bit $(1$ gate$/$bit$).$

e$)$ Assuming $D$ flip$-$flops to store each bit $(4$ gates$/$flip$-$flop$).$ What $\%$ of the total gates is used to implement the $D$ flip$-$flops? The formula for this would be:

$\frac{\text{T}\text{o}\text{t}\text{a}\text{l}\text{n}\text{u}\text{m}\text{b}\text{e}\text{r}of\text{g}\text{a}\text{t}\text{e}\text{s}\text{f}\text{o}\text{r}\text{t}\text{h}\text{e}D\text{f}\text{l}\text{i}\text{p}-\text{f}\text{l}\text{o}\text{p}\text{s}}{\text{T}\text{o}\text{t}\text{a}\text{l}\text{n}\text{u}\text{m}\text{b}\text{e}\text{r}of\text{g}\text{a}\text{t}\text{e}\text{s}\text{f}\text{o}\text{r}D\text{f}\text{l}\text{i}\text{p}-\text{f}\text{l}\text{o}\text{p}\text{s}+\text{T}\text{o}\text{t}\text{a}\text{l}\text{f}\text{o}\text{r}\text{t}\text{h}\text{e}\text{M}\text{U}\text{X}(s)+\text{T}\text{o}\text{t}\text{a}\text{l}\text{f}\text{o}\text{r}\text{t}\text{h}\text{e}\text{D}\text{e}\text{c}\text{o}\text{d}\text{e}\text{r}(s)}100$

Redo the previous question using the $1G8$ square$-$memory implementation similar to the "Implementation of Large Memory Chips" section of Supplement #$5.$ For part $($e$),$ assume dynamic memory is used to store each bit $(1$ gate$/$bit$).$