7. [50 points] The following two figures show the format of an x64 (64-bit superset of the x86 architecture supported by AMD and Intel) virtual address, and the format of an x64 page table entry Page map vel Page directory Page table Page table entry Byte within selector 4 selector inter selector selector 9 bits 9 bits 9 bits 9 bits 12 bits 63 62 52 51 32 Physical-Page Base Address This is an architectural limit. A given implementation may support fewer bils.) Reserved, MBZ Physical-Page Base Address a. What is the page size of this architecture? b. Can you think of reasons why current implementations of the x86 architecture limit the number of bits to 48 (=12+9+9+9+9)? c. What is the total size of each table (page map table, page directory table, page table selector table, page table)? d. What are the advantages of a multi-level page table approach