$8\mathrm{.}6$ Design a circuit to implement the truth table shown in Fig. P$8\mathrm{.}6.$ A gate$-$level design is sufficient.

$8\mathrm{.}7$ The circuit you have designed in Problem $8\mathrm{.}6$ is embedded in the larger circuit shown in Fig. P$8\mathrm{.}7.$ Complete the timing diagram for the output.

$8\mathrm{.}8$ The voltage waveforms shown in Fig P$8\mathrm{.}8$ are applied to the nMOS JK master$-$slave flip$-$flop shown in Fig. $8\mathrm{.}23.$ With the flip$-$flop initially reset, show the resulting waveforms at nodes $Q_m($master flip$-$flop output$)$ and $Q_s($slave flip$-$flop output$).$

$\backslash$table$[[S,R,Q,\frac{?}{\text{b}\text{a}\text{r}}(Q)$