8. A pipelined CPU contains a sequence of 5 stages: F, D, E, M, W. The...

 

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8. A pipelined CPU contains a sequence of 5 stages: F, D, E, M, W. The delay through the F and D stages is 180 ps each, whereas the delay through the other stages is 230 ps each; the pipeline registers have a delay of 20 ps each. a. What is the highest frequency clock which can be used to safely clock the pipeline. b. Assuming that CPU registers are read by the D stage and written by the w stage, what is the shortest time in which the following sequence of instructions can be executed. movq $3, %rcx $4, %rbx %rcx, %rbx movq addq movq $0xAAAA, %rcx andq %rcx, %rbx Assuming that dependencies are handled by stalling the pipeline, provide the total time from when the first instruction enters the pipeline to when the last instruction completes fully. 15-points 8. A pipelined CPU contains a sequence of 5 stages: F, D, E, M, W. The delay through the F and D stages is 180 ps each, whereas the delay through the other stages is 230 ps each; the pipeline registers have a delay of 20 ps each. a. What is the highest frequency clock which can be used to safely clock the pipeline. b. Assuming that CPU registers are read by the D stage and written by the w stage, what is the shortest time in which the following sequence of instructions can be executed. movq $3, %rcx $4, %rbx %rcx, %rbx movq addq movq $0xAAAA, %rcx andq %rcx, %rbx Assuming that dependencies are handled by stalling the pipeline, provide the total time from when the first instruction enters the pipeline to when the last instruction completes fully. 15-points