8 -. Based on 1K 8 RAM with address lines Ao-A, (see Fig. 4(a)) and one 2-to-4 decoder with negative output -ee Fig. 4(b)), please design 2K*16 RAM when the input A of 2-to-4 decoder is connected to LOW voltage te: you should clearly mark A.-Alo and show how to connect Yo-Y3). (13%) Input Data 8 IK X 8 RAM Address 10 2-to-4 Output Ao-Ag Data decoder Chip Select A 2 B 2 Read/Write (b) Fig. 4: (a) 1K 8 RAM (6) 2-to-4 decoder 8 -. Based on 1K 8 RAM with address lines Ao-A, (see Fig. 4(a)) and one 2-to-4 decoder with negative output -ee Fig. 4(b)), please design 2K*16 RAM when the input A of 2-to-4 decoder is connected to LOW voltage te: you should clearly mark A.-Alo and show how to connect Yo-Y3). (13%) Input Data 8 IK X 8 RAM Address 10 2-to-4 Output Ao-Ag Data decoder Chip Select A 2 B 2 Read/Write (b) Fig. 4: (a) 1K 8 RAM (6) 2-to-4 decoder