$9\mathrm{.}16$ Memory Elements

Description

Create a four bit register using only D flip flops. The register should load values at the positive edge of the clk$.$ Inputs: D $-4$ bits, CLK $-1$ bit

Outputs: Q $-4$ bits,

Useful Syntax

Always block:

The always block executes every time a variable in it's sensitivity list changes value.

Syntax:

always@$(//)$ begin

I NEED HELP WITH THIS VERILOG CODE, I HAVE TRIED ALL KINDS OF CODES AND NOTHING GIVES ME THE OUTCOMES $5/5.$ PLEASE HELP!!!!