$9.$ Consider a generic byte addressable memory hierarchy consisting of the following: $$ a $64-$bit virtual address space, a direct$-$mapped L$1$ I$-$cache containing $512$ blocks with each block containing $64$ bytes, and a $16$K byte $2-$way set associative L$1$ D$-$cache with each block containing $128$ bytes; $$ a $3$M byte $3-$way set$-$associative L$2$ cache with a block size of $512$ bytes; $$ a $10$M byte fully$-$associative L$3$ cache with a block size of $512$ bytes; $$ a segmented$-$paged virtual memory $(48$GB physical memory space, $64$ segments, $8$K pages, using an LRU page replacement policy $,$ and a $8$GB swap disk$)$; and $$ a hypervisor re$-$mapping of physical pages to actual pages $($also $8$K$)$ that uses nested page tables. Assume that the caches all use real addresses. $($a$)(4$ points$)$ Illustrate the address translation process. $($b$)(9$ points$)$ Define the sizes of the fields in the $($i$)$ virtual, $($ii$)$ physical, and $($iii$)$ real addresses. Document how these sizes are determined. $($c$)(6$ points$)$ Document how these sizes of the virtual, physical, and real addresses are determined. $($d$)(15$ points$)$ Show the decomposition of the cache addresses for cache lookup $($you should be showing the decomposition of $4$ addresses$).$ Basically I$$m asking you to draw a rectangle for each address and show how the bits in each address $($rectangle$)$ are separated and used to lookup$/$process that address.