9. Suppose we have a processor with a base CPI of 1, assuming all references hit in the primary cache. Consider a two-level cache, where the miss rates per instruction at the primary cache and the secondary cache are 5% and 1%, respectively. Suppose the miss penalties for an access to the main memory and the secondary cache are 100 and 10 clock cycles, respectively. (10%) (a) What is the effective CPI for a one-level cache where only the primary cache is used without the secondary cache? (5%) (b) What is the effective CPI for a two-level cache where both the primary cache and the secondary cache are used? (5%)