9. Suppose we want to execute the following code segment on the pipelined CPU: add $2,...

 

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9. Suppose we want to execute the following code segment on the pipelined CPU: add $2, $5, $4 add $4, $2, $5 lw $5, 100 ($2) add $3, $2, $5 Suppose there is no hardware supports for the forwarding and the stalling, but the register file can be written at the first half of a cycle and be read at the second half. (A) How many NOPs and at what places that you can add to make the code segment (8%) execute correctly on our pipeline? (B) Suppose the pipeline stalls, but no forwards, when there is data hazard. How many (4%) cycles will the above code segment execute? 9. Suppose we want to execute the following code segment on the pipelined CPU: add $2, $5, $4 add $4, $2, $5 lw $5, 100 ($2) add $3, $2, $5 Suppose there is no hardware supports for the forwarding and the stalling, but the register file can be written at the first half of a cycle and be read at the second half. (A) How many NOPs and at what places that you can add to make the code segment (8%) execute correctly on our pipeline? (B) Suppose the pipeline stalls, but no forwards, when there is data hazard. How many (4%) cycles will the above code segment execute?

Answer rating: 100% (QA)

To answer this question lets analyze the provided code segment and look for data hazards that would require the introduction of NOPs No OPeration inst... View the full answer