$9.$ When an interrupt occurs, control must be transferred from the currently executing program to

a subroutine $($the ISR$)$ that handles the activity required to service the interrupt. For each

interrupt, a $$context switch$$ is said to occur. Each context switch incudes transferring control as

well as saving or restoring any required registers. Assume that it takes $1000$ clock cycles to

perform each context switch when an I$/$O device triggers an interrupt. The interrupt service

routine $($ISR$)$ takes an additional $2,000$ cycles to service the device request. Once the device has

been serviced, the context switch needed to return from the interrupt handler back to the program

that was running also takes $1000$ cycles. The CPU clock rate is $1$ GHz$.$

a$)(4)$ What is the maximum number of requests per second that a device can generate if the

system must complete all activity associated with each interrupt, including the context switches,

before the next interrupt occurs?

b$)(4)$ Interrupt driven I$/$O is used for a different device that issues $10000$ evenly spaced requests

per second and transfers $1$ byte per request. A total of $4000$ clock cycles are required to handle

each interrupt. Each instruction takes one clock cycle to execute. Part of each second is

consumed in handling interrupts. How many instructions can be executed in the remaining part

of each second that is not consumed by context switches and executing the interrupt handler?

c$)(4)$ Suppose that instead of interrupt driven I$/$O$,$ DMA is used to transfer one data block each

second. Each data block contains $10000$ bytes of data. With DMA, it takes $5000$ clock cycles to

setup and manage each block transfer including the context switches and interrupt handler. Each

instruction takes one clock cycle. How many instructions other than those required for I$/$O can

the CPU execute each second?