$A110$

$A120$

$A130$

$2)(10$ points$)$ Next, add a $16$K program ROM unit corresponding to the memory address range $C$000$ to $FFFF$.$ Show the logic to generate the CE signal$($s$)$ for this ROM, which should be active low, if two $8$K x $8$ ROM chips are used. Draw and test the complete circuit in Logisim within the $"$Q$2"$ subcircuit in the provided file, using traditional logic gates.

$($Hint: Again, an $8$K x $8$ memory chip has a capacity of $8192$ bytes, so you will need to use an array of two of these chips to create a single $16$K x $8$ memory unit, which has a total capacity of $16384$ bytes. The chip$-$enable signal $!$CE$0$ should be active in the lower half of this address range, and the chip$-$enable signal $!$CE$1$ should be active in the upper half of this address range.$)$