A 2-bit binary comparator designed by using synchronous state machine has two outputs. The outputs are always
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A 2-bit binary comparator designed by using synchronous state machine has two outputs. The outputs are always equal to (00) unless one of the following cases occurs: 1. If the present input value is greater than the previous input value, the first and second outputs are logic "1" and logic 0", respectively. 2. If the present input value is less than the previous input value, the first and second outputs are logic "O" and logic 1", respectively. How many states are required to draw minimal Mealy state diagram for the aforementioned state machine?
Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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