A $32-$bit $1\mathrm{.}6$ GHz $($i$.$e$.$ clock speed is $1\mathrm{.}6$ GHz $)$ computing system has a half word addressable memory with $40-$bit address bus. This memory takes $2$ clock cycles to complete read or write operation and processor takes $1$ clock cycle to consume data from memory. During operation, with a single instruction, the processor generated $2\mathrm{.}5$ million $(1$ million $={10}^6)$ continuous read$/$write operation request. $40\%$ of memory operations are read operations. $20\%$ of the write operation requests are successor to a read operation request. $[$Note: this type of memory access is known as DMA $($Direct Memory Access$)$ and not included in our study$]$

Calculate clock period in ns unit. $[3$pts$]$

Calculate memory size in GB unit. $[5$pts$]$

How long will it take to complete this $2\mathrm{.}5$ million memory access in ms unit? $[12$pts$]$