A$.(4$ points$)$

Draw a compound gate $($in transistor level$)$ that implements the function described below. Find the Complex AOI

minimum sizing of the transistors. Calculate the parasitic delay and logical effort of the gate inputs.

B$.(3$ points$)$

What is the value of sequencing overhead for a Flip$-$Flops design. Use the values of the table below in your calculation.

TABLE I

Different Delay Parameters

$\backslash$table$[[t_{pl},10$ ns$],[t_{ed},8$ ns$],[t_E,1$ ns$],[t_{898},0\mathrm{.}05$ ng$],[$taetup$,1$ ns$],[t_{\text{h}\text{a}\text{l}\text{a}},1\mathrm{.}5$ n$]]$

Parasitic delay of common gates.

$\backslash$table$[[$Gate Type,Number of lnputs$],[,1,2,3,4,n$