$($a$)(5$ points$)$ What is the logic function implemented by the gate in the above figure?

$Y=$

$($b$)(10$ points$)$ Draw the PMOS network:

$($c$)(10$ points$)$ Determine the size of the transistors if the reference CMOS inverter is $(\frac{W}{L}{)}_N=\frac{2}{1}$ and $(\frac{W}{L}{)}_P=\frac{4}{1}.$ You can write your answer on the schematics above.

$($d$)(5$ points$)$ What would the $\frac{W}{L}$ ratios be if the reference CMOS inverter from the last part were to have a a propagation delay, $\frac{}{4},$ relative to the original design?