a) A four-processor shared-memory system implements the MESI protocol for addressing the cache coherence. Consider the sequence of memory references, as specified in the first column of Table 4. PO's Cache PI's Cache P2's Cache P3's Cache Memory Line (where Line (where Line (where Line (where State variable a is variable a is variable a is variable a is mapped) mapped) mapped) mapped) Hit/ Miss E I 1 I Valid N/A Starting state PO reads a P1 writes a P1 reads a PO Reads a P2 Reads a P3 writes a Table 4: Status of each processor's cache line where variable a is mapped Show the states (M, I, E or S) of the cache line containing the variable a in each processors (PO, P1, P2, P3) cache after each reference is resolved. Each processor's starting state is shown in the second row of Table 4. Also, show the state of the memory (valid or out of date) in the Memory state column of the Table 4. In the last column of Table 4, identify whether the access is a hit or a miss. b) Considering a given state (defined in the different columns of Table 5) of the MESI protocol for a processor's cache C1, answer the questions given in the first column of Table 5. Modified Exclusive Shared Invalid Copies exists in other caches? Table 5: States in MESI protocol Write Yes, No, or Not known into the relevant cells of Table 5. [4 marks) a) A four-processor shared-memory system implements the MESI protocol for addressing the cache coherence. Consider the sequence of memory references, as specified in the first column of Table 4. PO's Cache PI's Cache P2's Cache P3's Cache Memory Line (where Line (where Line (where Line (where State variable a is variable a is variable a is variable a is mapped) mapped) mapped) mapped) Hit/ Miss E I 1 I Valid N/A Starting state PO reads a P1 writes a P1 reads a PO Reads a P2 Reads a P3 writes a Table 4: Status of each processor's cache line where variable a is mapped Show the states (M, I, E or S) of the cache line containing the variable a in each processors (PO, P1, P2, P3) cache after each reference is resolved. Each processor's starting state is shown in the second row of Table 4. Also, show the state of the memory (valid or out of date) in the Memory state column of the Table 4. In the last column of Table 4, identify whether the access is a hit or a miss. b) Considering a given state (defined in the different columns of Table 5) of the MESI protocol for a processor's cache C1, answer the questions given in the first column of Table 5. Modified Exclusive Shared Invalid Copies exists in other caches? Table 5: States in MESI protocol Write Yes, No, or Not known into the relevant cells of Table 5. [4 marks)