a.) A pipeline machine with clock cycle time 10ns, CPI of 1.6 and 90% accurate branch prediction. The miss- prediction penalty is two cycles and that 10% of the instructions are branches. A new processor is designed with clock cycle time of 9ns with miss-prediction penalty of five cycles and all other parameters are the same. Is the new processor faster or slower than the old one explain? b.) A program instructions are 10% lw with 7 cycles latency, 15% sw with 10 cycles latency, 15% beq with 4 cycles latency, 55% add with 4 cycles latency, 5% logic op with 4 cycles latency. What is the CPI for this processor? c.) If you can halve the cycle latency of any single category of part b instructions and increase the clock cycle time by 20% which category of instruction should you speed up? If there is a speedup, then what is the CPI of the new design?