a$)$ An embedded system using a microcontroller$($Eg: Motorola $68$HC$12$ microcontroller$)$ with $16$ address lines

has a byte addressable$/$organized memory. The main memory is of the maximum allowable limit$.$ It has a

direct mapped data cache, with $8$ lines, with each line consisting of $16$ bytes. How many bits of address are

used for the tag fields? What is the size of the cache $($used only for storing data$)$

b$)$ In an IoT system, which utilizes cache, If we want an average memory access time of $6\mathrm{.}5$ ns$,$ if cache

access time is $5$ns$,$ and the main memory access time is $80$ ns$,$ what cache hit rate must we achieve for the

cache implementation to be worthwhile?

c$)$ Mention the steps involved in a Write back, write allocate cache when the $$STR R$1,[$R$2]$ instruction is

executed $.$ Assume that the instruction cause write miss.