A byte$-$addressable CPU requires to address $4$ GB of Main memory, $512$ MB

$($only data size$)$ of Cache memory. Each cache block contains $1$ K bytes. For

each of the following cache configurations,

i$)$ Direct mapped

ii$)64-$way set associative

iii$)$ Fully associative

Specify how the physical address would be partitioned into TAG, INDEX,

OFFSET for each of the above mappings. Also design the cache and calculate

the total cache size requirement including the overhead information.