A carry look ahead generator circuit helps speed the process of adding binary numbers by

calculating the carry bits before the addition process begins. Assuming a $6-$bit adder, and by

using Verilog design and testing:

$1)$ Show how fast is the carry look ahead compared to the serial adder. Assume that the

propagation delay of any logic gate used $($ AND, NAND, OR$,$ NOR, NOT, XOR, XNOR$)$ is

$10$ns$.$

$2)$ Test the circuit by performing $3$ tests on adding different numbers of your choice.

to solve it you should write verilog code and test benc for it and dont forget to add propagation delay