A certain computer has a memory system made up of four separate memory modules or chips. Each module has a width of $8$ bits per cell and a depth of $16777216.$ The system contains a separate address bus and a separate data bus. The address bus and data bus are shared by the memory modules. On this system, memory accesses must be aligned and are performed in two phases.

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To read a memory cell on this system, an address must be sent over the address bus. The address must contain the module number and cell number. The selected module saves or latches the cell number on its address pins after which it releases the address bus. Once released, the address bus is free to be used for a transaction with a different memory module. $$Forty nanoseconds are required to complete this first phase, the addressing phase.

Forty nanoseconds are also required by the selected module to acquire the bits contained in the selected cell and transfer them over the shared $8-$bit data bus. This second phase is called the data transfer phase.

One way to improve performance when reading multiple cells from different memory modules is to $$pipeline$$ the memory accesses by overlapping the addressing phase for one memory module with the data transfer phase of a different memory module.

Recall that an individual module can only perform one read or write at a time and the address used by a module must not change before the data transfer phase for that module completes. Answer the following questions assuming the address bus and data bus operations are overlapped in this fashion.