A combination lock has a reset input RESET, two inputs b0 and b1, one for 0 and one for 1, respectively, and an unlock output unlock. In reality, inputs are asynchronous signals, but assume that they are synchronous. (a) Draw the finite state machine for your design. Is this a Moore machine or a Mealy machine? (b) Write a Verilog module using a finite state machine (FSM) to simulate a combination lock that would unlock if the input sequence is 01001. (c) Write a testbench for your design. Present the output waveform of your design using the following input sequence 0001001011. Include the input/output signals along with the state variable in the output waveforms.