A computer engineer is designing a cache memory system for a computer processor with a 64-bit address
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A computer engineer is designing a cache memory system for a computer processor with a 64-bit address space.
a) Calculate the number of cache sets in the cache memory if the cache size is 512 KB, the block size is 64 bytes, and the set associativity is 4-way.
b) Calculate the number of tag bits required for the cache memory if the cache size is 512 KB, the block size is 64 bytes, and the set associativity is 4-way.
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Related Book For 
Computer Organization and Design The Hardware Software Interface
ISBN: 978-0124077263
5th edition
Authors: David A. Patterson, John L. Hennessy
Posted Date:
