A computer system has byte-addressable memory and uses a paged virtual memory system, using 128-byte pages. It uses a 16-bit virtual address and a 14-bit physical address. Its Translation Lookaside Buffer (TLB) is 4-way set-associative and has a total of 16 entries. It uses an L1 cache which is physically addressed and direct mapped, with 4 bytes per cache line and a total of 16 cache sets.

a) Show how the virtual address is divided between the Virtual Page Number and the Virtual Page Offset.

b) Show which bits of the virtual address are used and how they are used for accessing the TLB.

c) Show which bits of the physical address are used for the Physical Page Number and the Physical Page Offset.

d) Show which bits of the physical address are used and how they are used when looking for the data in the L1 cache.

e) Given a virtual address 0xA234

i. What is the Virtual Page Number?

ii. What is the Virtual Page Offset?

iii. What is the TLB index?

iv. What is the TLB tag?