A computer system with a well-designed CPU and a poorly designed memory subsystem will have a poor effective performance. You are currently working on a custom experimental 64KB DRAM chip design for the smart glasses system. 1) Briefly discuss how a memory sub-system can be a performance bottleneck in the smart glasses system. [4] 2) Briefly explain what is meant by temporal and spatial locality of reference. Use brief C/C++ code snippets to illustrate. [6] 3) The 64KB chip can be designed either as a single 64KB chip or in a modular scheme using either low or high-order memory interleaving. Assume that smaller 8K x 8 chips can be sourced from another company. a) Briefly explain why an interleaved implementation could be the better option. [2] b) Between low-order and high-order interleaving, which one is most suitable given the target system. Explain. [2] c) How many of the smaller 8K x 8 chips are required? [2] d) How many address lines are required for the 64KB chip? [2] e) Show, using a simple sketch, how the 8K x 8 chips will be connected using a suitable decoder to construct the larger 64KB chip. [4]