a) Consider a hypothetical four stage processor where the stages are defined as: sl, s2, 53, 4. Each stage requires 1 cycle to complete. Suppose a program consisting of 300 instructions, is executed on this 4-stage processor. i) Draw the timing diagram showing the execution of the first four instructions, considering that the program is running on without pipelining, 14 marks) ii) Draw the timing diagram showing the execution of the first four instructions, considering that the program is running with ideal pipelining. Assume that there is no pipeline hazards and dependencies. 14 marks] 1) Compute the execution time of the program without pipelining and with pipelining (no dependencies), and compare the performance improvement for ideal pipelining. 14 marks! iv) Consider that the program is running with pipelining, but there are some dependencies. Each instruction is dependent on a specific stage of the instruction immediately before it, particularly stage 52 of cach instruction is dependent on stage 3 of the instruction immediately before it. That is: stage s2 of instruction two is dependent on stage s3 of instruction one, stage s2 of instruction three is dependent on stage 53 of instruction two and so on... To address the hazard created by the dependencies assume that the pipeline will be stalled until the hazard is cleared. No forwarding or other options are available to avoid the hazard. Draw the pipeline timing diagram showing the execution of the first four instructions. Indicate the stall (wherever required) by using a "x" in the corresponding pipeline stage 14 marks] Use the observations from this timing diagram to determine the cycle per instruction (CPI). Show your working 14 marks