a. Consider the scenario where 8259 Programmable Interrupt Controller (master) is interfaced with 8088 microprocessor at address B2h-B3h. This master 8259 PIC has one slave 8259 PIC, connected at IR4. Slave 8259 PIC is interfaced at address C8h-C9h. Further details are:

Interrupt request inputs are edge triggered for both 8259s. Special Fully Nested mode is selected for master 8259 only. Normal End of Interrupt is selected for both 8259s. Buffered Mode is used. For the given scenario, write the pattern for initialization command words (ICW1 and ICW4) with reasoning and instructions to load these command words for both 8259s.

a. Consider the scenario where 8259 Programmable Interrupt Controller (master) is interfaced with 8088 microprocessor at address B2h-13h. This master 8259 PIC has one slave 8259 PIC, connected at TR4. Slave 8259 PIC is interfaced at address C8h-C9h. Further details are: Interrupt request inputs are edge triggered for both 8259s. Special Fully Nested mode is selected for master 8259 only. Normal End of Interrupt is selected for both 8259s. Buffered Mode is used. For the given scenario, write the pattern for initialization command words (ICW1 and ICW4) with reasoning and instructions to load these command words for both 82598. [6] ICWI: LTIM SNGL IC4 ICW4 0 0 0 SFNM BUF MS AEOI UPM a. Consider the scenario where 8259 Programmable Interrupt Controller (master) is interfaced with 8088 microprocessor at address B2h-13h. This master 8259 PIC has one slave 8259 PIC, connected at TR4. Slave 8259 PIC is interfaced at address C8h-C9h. Further details are: Interrupt request inputs are edge triggered for both 8259s. Special Fully Nested mode is selected for master 8259 only. Normal End of Interrupt is selected for both 8259s. Buffered Mode is used. For the given scenario, write the pattern for initialization command words (ICW1 and ICW4) with reasoning and instructions to load these command words for both 82598. [6] ICWI: LTIM SNGL IC4 ICW4 0 0 0 SFNM BUF MS AEOI UPM