Question: (a) Construct the ASM chart for the given algorithm. (b) Design the controller for the ASM using a minimum number of D type flip-flops. (c)
(a) Construct the ASM chart for the given algorithm.
(b) Design the controller for the ASM using a minimum number of D type flip-flops.
(c) Design the minimal datapath for the ASM and define all control input functions of the datapath.
(d) Assume that at the initial clock cycle C0, state is Init. Input X becomes logic 1 in clock cycle C0 and stays as logic 1 for 1 clock cycle then resets to logic 0. Compute and write-in total number of clock cycles to return the Init state after leaving the Init state. For example, for a sample state transition sequence Init -> Run1 -> Run1 -> Init, total number of clock cycles to return Init is 3.
procedure ASM(X,R)
Init:
if X = 0 then
R <-- 3
go to Init
else
R <-- 49
go to Run1
endif
Run1:
R <-- R - 7
if R < 4 then
go to Init
else if X = 1 then
go to Run1
else
go to Run2
endif
Run2:
R <-- R - 2
if R < 2 then
go to Init
else if X = 1 then
go to Run1
else
go to Run2
endif
end procedure
Step by Step Solution
There are 3 Steps involved in it
Get step-by-step solutions from verified subject matter experts
Study Help