(A) Construct the fuse map for a PAL circuit showing the implementation of the following Logic functions:

= + + +

= + + + +

= + + C

(B)

A counter has the following sequence 6, 5, 4, 3, 2, 1. Design a synchronous Logic circuit to generate this sequence using positive edge-triggered JK flip-flops and any suitable logic gates. The design should include the following:

(i) The State Diagram. (1 Mark)

(ii) Next state table. (1 Mark)

(iii) The Excitation Table. (2 Marks)

(iv)Derivation of the minimized logic expressions for the flip-flop inputs using Karnaugh maps.

(v) The logic circuit diagram. (5 Marks)

(vi) Next state table of the un-used states. (2 Marks)

(vii) State diagram including the un-used states using the results in part

(viii) The timing diagram.