A counter with RST (reset) and DIR (direction) inputs will be designed. When RST = 0 and DIR = 0 (..0,2,4,0 .. or ..1,3,5,1 ..), TWO FORWARD and when RST = 0 and DIR = 1 (... 0, 5,4,3,2,1,0,5 ..). When RST = 1, the counter will go to "0" regardless of DIR and. As long as RST = 1, it will stay there. When RST = 0, it will continue in accordance with DIR. Also, when the Number is 0, the OVR (Overflow) output will be 1, otherwise it will be 0.

a) How many Flip-Flops will you need to use in your design? Explain.

b) Create the state transition diagram and table of the system.

c) You will implement the system using T flip-flops. Realize the necessary Next State logic circuit using Multiplexers.

d) Let us assume that the frequency of the CLOCK signal used in the counter is 300kHz and the counter is at "0".