$($a$)$ Design a $3$bit equality comparator which outputs logic $1$ if the two $3-$bit numbers $x_2{x}_1{x}_0$ and $Y_2{Y}_1{Y}_0$ are equal. Design using only one $3$:$8$ Decoders and only one $8$: $1$ MUX.

$($b$)$ A Combinational logic circuit is to be designed which can shift a $4-$bit number to the left or right by $n$ bits depending on the control as given below.

Control:

$00,$ Shift right by $1$ bit position

$01$ Shift right by $2$ bit position

$10$ Shift left by $1$ bit position

$11$ Shift left by $2$ bit position

After shift the vacant positions are filled by $1.$ Ex: if input number $1011$ and control $11$ then output number is $1111$ and if control is $01$ then the output number is $1110.$

Design the shifter only using multiplexers of required size and number $($Design should use optimum number of multiplexers$)$