a. Design a system with an 8-bit input I that can be stored in 8-bit registers A, B, and/or C when control input La, Lb, and/ork is respectively. For example, if inputs La and Lb are '1', and Le is '0', then registers A and B will be loaded with input I, but register C will keep its current value. Furthermore, if input R is '1', then the register values rotate such that A-B, B-C, and C-A. Input R has priority over the L inputs. The system also has one clock input connected to the clock input of the three registers. Draw your system using gates, 8-bit registers with clock and load inputs, and 8-bit 2-to-1 multiplexers. A data path can be shown as an 8-bit bus: 8 b. Write the VHDL code for your system. Create a single module entity with inputs of I, R, La, Lb, Lc and three outputs which are the outputs of the three registers. Use a single level hierarchy. Your code should have three processes, one for each register with its associated mux and logic. (See "VHDL for Multifunction Register with functional control signals" in the lecture notes)