A digital system is modelled by the RTL code in Listing Q1. Assume that a, b...

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A digital system is modelled by the RTL code in Listing Q1. Assume that a, b and c are external inputs, and the registers are positive-edge triggered. By using the ALU with the functions given in Table Q1, answer the following questions. Note that m* denotes m bitwise inverted. SO: () /R1 b; Table Q1: ALU operation (a) ( ) /R2 C fifo output function S1: ( ) /R2 R1 R2; 00 X+Y ADD ( ) /R1a; 01 X-Y SUB S2: (m) /R2 <2R1; 10 X*Y Multiply (m) /R2R1-R2; 11 Y PASS Y ( ) / done = 1; ( ) / goto SO; Listing Q1: RTL code Derive the functional block diagram (fbd) of the datapath unit (DU) for the digital system in Q1. (8 marks) (b) Write the Verilog code to model the datapath in Q1(a). (9 marks) (c) Derive the fbd of the control unit (CU) showing the state registers, next state block. output block and all the control signals. Note: Group the control signals as a vector formatted as follows: sell, sel2, selY, Idl, ld2.fl.fo. done. (6 marks) (d) (e) Write the Verilog code to model the control unit in Q1(c). The control vector must be formatted as in Q1(c). (9 marks) If the multiply function is not available in the ALU, suggest an option to implement the operation of R2R1 R2 in state S1 if Y input is limited to 2, 4 and 8. (3 marks) A digital system is modelled by the RTL code in Listing Q1. Assume that a, b and c are external inputs, and the registers are positive-edge triggered. By using the ALU with the functions given in Table Q1, answer the following questions. Note that m* denotes m bitwise inverted. SO: () /R1 b; Table Q1: ALU operation (a) ( ) /R2 C fifo output function S1: ( ) /R2 R1 R2; 00 X+Y ADD ( ) /R1a; 01 X-Y SUB S2: (m) /R2 <2R1; 10 X*Y Multiply (m) /R2R1-R2; 11 Y PASS Y ( ) / done = 1; ( ) / goto SO; Listing Q1: RTL code Derive the functional block diagram (fbd) of the datapath unit (DU) for the digital system in Q1. (8 marks) (b) Write the Verilog code to model the datapath in Q1(a). (9 marks) (c) Derive the fbd of the control unit (CU) showing the state registers, next state block. output block and all the control signals. Note: Group the control signals as a vector formatted as follows: sell, sel2, selY, Idl, ld2.fl.fo. done. (6 marks) (d) (e) Write the Verilog code to model the control unit in Q1(c). The control vector must be formatted as in Q1(c). (9 marks) If the multiply function is not available in the ALU, suggest an option to implement the operation of R2R1 R2 in state S1 if Y input is limited to 2, 4 and 8. (3 marks)