A digital system-on-chip is composed of logic gates and memory array and has the following break down with the associated properties in the table below: Assume that 1/2 transistors have subthreshold leakage and 1/2 transistors have gate leakage. a) Calculate the width of all transistors that have high leakage? b) Calculate the width of all transistors that have low leakage? c) Estimate the static power consumption of the system. d) How would the power consumption change if the low-leakage devices were not available