A DRAM main memory system has N banks in one rank on one channel. A row is 256 bytes and a cache block is 64 bytes. Data is row-interleaved across banks using the following physical address bit scheme: (Row: Rank: Column: Byte Offset).

An open row policy is used, i.e., a row is retained in the row-buffer after an access until an access to another row is made. Initially, row 1024 is open in all banks in all channels.

a. Determine the total number of banks (across all channels) in the system given that the row-buffer hit rate on the following sequence of cache block numbers is 33.3% (1/3) Sequence: 0, 4, 8, 16, 32, 64, 128, 256, 128, 64, 32, 16, 8, 4, 0.

b. For what total number of banks in the system will the row-buffer hit rate of this sequence be 7/15?