a) Draw the ASM chart for the module above. b) Explain very clearly what this program...

 

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a) Draw the ASM chart for the module above. b) Explain very clearly what this program actually does. module test(y, x, reset, clock); output y input x, clock ,resel; reg y; reg [1:0] state, next_state; parameter S0-2'600, S1-2'b01, S2-2'b10, S3-2'b11; always @ (posedge clock or negedge reset) if (reset==0) state<=S0; else state<= next_state; always @ (state, x) case (state) SO: $1: if (x) next_state = $1; else next_state = S0; if (x) next_state = S3; else next_state = S0; if (-x) next_state = S0; else next_state = S2; S3: if (x) next_state = S2; else next_state = S0; endcase S2: always @ (state, x) case (state) SO: $1, S2, S3: endcase endmodule y=0; y=~x; a) Draw the ASM chart for the module above. b) Explain very clearly what this program actually does. module test(y, x, reset, clock); output y input x, clock ,resel; reg y; reg [1:0] state, next_state; parameter S0-2'600, S1-2'b01, S2-2'b10, S3-2'b11; always @ (posedge clock or negedge reset) if (reset==0) state<=S0; else state<= next_state; always @ (state, x) case (state) SO: $1: S2: if (x) next_state = $1; else next_state = S0; if (x) next_state = S3; else next_state = S0; if(-x) next_state = S0; else next_state = S2; S3: if (x) next_state = S2; else next_state = S0; endcase always @ (state, x) case (state) SO: $1, S2, S3: endcase endmodule y=0; y=~x; a) Draw the ASM chart for the module above. b) Explain very clearly what this program actually does. module test(y, x, reset, clock); output y input x, clock ,resel; reg y; reg [1:0] state, next_state; parameter S0-2'600, S1-2'b01, S2-2'b10, S3-2'b11; always @ (posedge clock or negedge reset) if (reset==0) state<=S0; else state<= next_state; always @ (state, x) case (state) SO: $1: if (x) next_state = $1; else next_state = S0; if (x) next_state = S3; else next_state = S0; if (-x) next_state = S0; else next_state = S2; S3: if (x) next_state = S2; else next_state = S0; endcase S2: always @ (state, x) case (state) SO: $1, S2, S3: endcase endmodule y=0; y=~x; a) Draw the ASM chart for the module above. b) Explain very clearly what this program actually does. module test(y, x, reset, clock); output y input x, clock ,resel; reg y; reg [1:0] state, next_state; parameter S0-2'600, S1-2'b01, S2-2'b10, S3-2'b11; always @ (posedge clock or negedge reset) if (reset==0) state<=S0; else state<= next_state; always @ (state, x) case (state) SO: $1: S2: if (x) next_state = $1; else next_state = S0; if (x) next_state = S3; else next_state = S0; if(-x) next_state = S0; else next_state = S2; S3: if (x) next_state = S2; else next_state = S0; endcase always @ (state, x) case (state) SO: $1, S2, S3: endcase endmodule y=0; y=~x;

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a The asm chart for the module is as below b The m... View the full answer