$($A$)$ Given a circuit with $4$ registers, $1$ OR gate between registers $1,2$ and $3$ and one XOR gate connected between register $3$ and $4($output of $4$ going as second input$).$ All delay times for every and each component where given. The clock is synchronous for all registers. Calculate Tmin and explain. $($B$)$ Is there any hold$-$time violation. Explain how to solve this problem. $($C$)$ A Delay block is put before the clock of register $3($also connected furtheron to register $4).$ How will this affect Tmin calculated in $($A$)$ and will this affect any hold$-$time violations calculated in $($B$).$