a$)$ In Brief with one example; i$)$ Identifiers and Keyword ii$)$ Net and Registers iii$)$ System task and Compiler Directives iv$)$ Parameter and Strings v$)$ Comment and Strings

b$)$ A $8-$bit parallel shift register has $\frac{1}{O}$ pins as shown in fig.

d

$t[7$:$0]$

c$|$

Write the module definition for this module shif$\_\_$reg. Include the list of ports and port declarations. You do not need to show the internals.

Declare a top$-$level module stimulus. Define DATA$\_$IN $(8$ bit$)$ and CLK $($I bit$)$ as reg register variables and DATA$\_$OUT $(8$ bit$)$ as wire. Instantiate the module shift$\_$reg and call it shreg $1.$ Connect the ports by ordered list and named list

III. Write the hierarchical names for DATA$\_$IN$,$ CLK and DATA$\_$OUT.