a) Indicate the time when N = 2 circuit signal becomes stable

b) Indicate the total cost of the N = 2 circuit

c) Complete the entity declaration fro an N-bit CSA

d) Complete the architecture definition of the CSA. Remember to include the gate delays in the VHDL model.

Thank you

8) N-bit Adder Circuit: An N-bit "conditional sum adder (CSA) is designed by applying the carry-select principle recursively. The number of operand bits, N, is assumed to be a power of two. The recursive stopping condition is applied for the case N = 2. Assume that all basic gates have a propagation delay of 1 ns and cost 1 . The Operands X, Y and Cin are stable at t=0 ns. a) Indicate the time when the N= 2 circuit signal become stable. | b) Indicate the total cost of the N = 2 circuit. Complete the entity declaration for an N-bit CSA. Complete the architecture definition of the CSA. Remember to include the gate delays in the VHDL model. N =2 X, Y. et Full Adder C C 'Mux le = te = S. X[N-1.#]Y[N-1.] Xqx_40) YH-L0] Caut -bit CSA CH 4-bit CSA c A ct -bit CSA CF aux ] c 'Mux S[N-1.11 SL-,01 b) 8) N-bit Adder Circuit: An N-bit "conditional sum adder (CSA) is designed by applying the carry-select principle recursively. The number of operand bits, N, is assumed to be a power of two. The recursive stopping condition is applied for the case N = 2. Assume that all basic gates have a propagation delay of 1 ns and cost 1 . The Operands X, Y and Cin are stable at t=0 ns. a) Indicate the time when the N= 2 circuit signal become stable. | b) Indicate the total cost of the N = 2 circuit. Complete the entity declaration for an N-bit CSA. Complete the architecture definition of the CSA. Remember to include the gate delays in the VHDL model. N =2 X, Y. et Full Adder C C 'Mux le = te = S. X[N-1.#]Y[N-1.] Xqx_40) YH-L0] Caut -bit CSA CH 4-bit CSA c A ct -bit CSA CF aux ] c 'Mux S[N-1.11 SL-,01 b)