$($a$)$ Instruction execution in a processor is divided into $5$ stages. Instruction Fetch $($IF$),$ Instruction Decode $($ID$),$ Operand Fetch $($OF$),$ Execution $($EX$)$ and Write Back $($WB$).$ These stages take $5,4,20,10$ and $3$ nanoseconds $($ns$),$ respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of $2ns.$ Two pipelined implementations of the processors are contemplated:

I. a na$$ve pipeline implementation $($NP$)$ with $5$ stages and

II$.$ an efficient pipeline $($EP$),$ where the OF stage is divided into stages OF$1$ and OF$2$ with execution times of $12ns$ and $8ns,$ respectively.

Calculate speedup $($correct to two decimals places$)$ achieved by EP over NP in executing $20$ independent instructions with no hazards. Draw space$-$time diagram also.