Question: A J - K flip - flop has a condition of J = 1 , K = 0 , Q = 0 , and both

A J-K flip-flop has a condition of J =1, K =0, Q =0, and both PRESET and CLEAR are active (for IC 7476, it is logic 0). If a 100-HZ clock pulse is applied to the CLK, the output Q+ is
(a)0
(b)1
(c)100 HZ
(d)50 HZ
(e) unpredictable

Step by Step Solution

There are 3 Steps involved in it

1 Expert Approved Answer
Step: 1 Unlock blur-text-image
Question Has Been Solved by an Expert!

Get step-by-step solutions from verified subject matter experts

Step: 2 Unlock
Step: 3 Unlock

Students Have Also Explored These Related Electrical Engineering Questions!